Communication Abstractions for System-Level Design and Synthesis

As we are entering the network-on-chip era and system communication is becoming a dominating factor, communication abstraction and synthesis are integral to defining system design flows and methodologies. The key to the success of any approach, however, are well-defined abstraction levels and models, which enable design automation for synthesis and verification to achieve the required productivity gains. In this report, we define a flow of system communication abstraction layers and corresponding design models that supports design automation for successive, step-wise refinement of communication from abstract application transactions down to a bus-functional implementation. We applied the flow to the example of a mobile baseband chip platform. Results show the trade-offs between accuracy and complexity of different transaction levels in the flow. Furthermore, the experiments demonstrate the effectiveness and feasibility of an automated flow.